1. Field of the Invention
This invention relates to a transistor with an offset gate structure, and more particularly to an improvement in the driving capability of a transistor with an offset gate structure.
2. Description of the Related Art
In MOSFETs, as their channel length become shorter, a short channel effect begins to take place, resulting in a fluctuation in the threshold value. For a MOSFET structure to alleviate the short channel effect, an LDD (Lightly Doped Drain) structure is widely known which has a reduced impurity concentration in the source/drain diffused layers, particularly in the vicinity of the gate electrode.
In LDD MOSFETs, the low impurity concentration at the edges of the diffused layers particularly in the vicinity of the gate electrode reduces an electric field strength there, which alleviates a short channel effect, improving the withstand voltage.
Even with such LDD MOSFETs, as their component elements get smaller, the withstand voltage decreases. A reduction in the withstand voltage is particularly significant when the gate length is smaller than or on the order of 0.6 to 0.4 .mu.m.
To solve this problem, an offset gate structure has been proposed which has a portion formed in the channel region at which the source/drain diffused layers and the gate electrode do not overlap each other.
These types of offset gate MOSFETs have an offset region in the current path (the channel region).
In the offset region, however, an inversion layer is not formed easily, thereby offering a high resistance. For this reason, offset gate MOSFETs cannot carry a sufficiently large current, which makes it difficult for the MOSFETs to sufficiently drive the transistors at the subsequent stage. That is, MOSFETs with an offset gate structure have a poor driving capability.